Hello world in System Verilog with line by line description

module top;

  initial begin
    $display("Hello World");
   end

endmodule

• Line 1 (module top;) : A "module" is the basic design unit of System Verilog, "top" signifies the name of the module. Every statement in System Verilog is ended by a semicolon.
• Line 2 ("initial begin") : "initial" is a  System Verilog construct simulator will start running everything written in initial block at time "0" of simulation.
• Line 3 ("$display("Hello World");") :  "$display" is a system task in System Verilog which is used to print anything to STDOUT.
• Line 4 ("end") : "end" signifies end of initial block.
• Line 5  ("endmodule") : "endmodule" signifies end of module "top".