CODE : 4 Bit Data Demultiplexer VHDL

CODE : 4 Bit Data Demultiplexer

This code is just an example for more detailed understanding of VHDL concepts I would recommend these two books :

1) A VHDL PRIMER by J. Bhasker - A VHDL PRIMER from flipkart.com
A VHDL PRIMER from amazon.com
A VHDL PRIMER from amazon.in

2)VHDL:PROGRAMMING BY EXAMPLES by PERRY - VHDL:PROGRAMMING BY EXAMPLES by PERRY from flipkart.com
VHDL:PROGRAMMING BY EXAMPLES by PERRY from amazon.com
VHDL:PROGRAMMING BY EXAMPLES by PERRY from amazon.in

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    10:47:38 11/06/2006
-- Design Name:
-- Module Name:    Demux_code - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Demux_code is
  port(  din   :in std_logic_vector(3 downto 0);
         sel   :in std_logic_vector(1 downto 0);
            dout1, dout2,dout3  :out std_logic_vector(3 downto 0));
end Demux_code;

architecture Behavioral of Demux_code is
begin
process(din,sel)
begin
    case sel is
        when "00"=> dout1<=din;
                    dout2<="ZZZZ";
                    dout3<="ZZZZ";
        when "01"=> dout1<="ZZZZ";
                    dout2<=din;
                    dout3<="ZZZZ";
        when others=>dout1<="ZZZZ";
                     dout2<="ZZZZ";
                     dout3<=din;
    end case;
end process;
end Behavioral;

CODE : BCD COUNTER VHDL

CODE : BCD COUNTER

This code is just an example for more detailed understanding of VHDL concepts I would recommend these two books :

1) A VHDL PRIMER by J. Bhasker - A VHDL PRIMER from flipkart.com
A VHDL PRIMER from amazon.com
A VHDL PRIMER from amazon.in

2)VHDL:PROGRAMMING BY EXAMPLES by PERRY - VHDL:PROGRAMMING BY EXAMPLES by PERRY from flipkart.com
VHDL:PROGRAMMING BY EXAMPLES by PERRY from amazon.com
VHDL:PROGRAMMING BY EXAMPLES by PERRY from amazon.in

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    23:45:17 11/01/2006
-- Design Name:
-- Module Name:    BCDcounter_code - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity BCDcounter_code is
    Port ( count:inout std_logic_vector(3 downto 0);
            clk  :in std_logic;
              rst  :in std_logic);
end BCDcounter_code;

architecture Behavioral of BCDcounter_code is
begin
process(clk,rst)
begin
    if rst='1' then
        count <= "0000";
    elsif clk'event and clk='1' then
        if count = "1001" then
            count <= "0000";
        else
            count <= (count+1);
        end if;
    end if;
end process;

end architecture;

CODE : TRAFFIC LIGHT CONTROLLER VHDL

CODE : TRAFFIC LIGHT CONTROLLER

This code is just an example for more detailed understanding of VHDL concepts I would recommend these two books :

1) A VHDL PRIMER by J. Bhasker - A VHDL PRIMER from flipkart.com
A VHDL PRIMER from amazon.com
A VHDL PRIMER from amazon.in

2)VHDL:PROGRAMMING BY EXAMPLES by PERRY - VHDL:PROGRAMMING BY EXAMPLES by PERRY from flipkart.com
VHDL:PROGRAMMING BY EXAMPLES by PERRY from amazon.com
VHDL:PROGRAMMING BY EXAMPLES by PERRY from amazon.in

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    00:24:35 11/02/2006
-- Design Name:
-- Module Name:    tfcontroller_code - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity tfcontroller_code is
    Port ( clk : in  STD_LOGIC;
           rst : in  STD_LOGIC;
           Green : out  STD_LOGIC;
           Red : out  STD_LOGIC;
           Yellow : out  STD_LOGIC);
end tfcontroller_code;

architecture Behavioral of tfcontroller_code is

signal count:integer range 0 to 10 := 0;
signal state:integer range 0 to 2 := 0;
begin
    process(clk, rst)
    begin
        if(rst = '1') then
            state <= 0;
            Red <= '1';
            Green <= '0';
            Yellow <= '0';
            count <= 0;
        elsif clk'event and clk='1' then
        case state is
        when 0 =>  --Red Light
        if(count=5) then
            count <= 0;
            state <= 1;
        else
            count <= (count + 1);
            Red <= '1';
            Green <= '0';
            Yellow <= '0';
        end if;
       
        when 1 =>  --Green Light
        if(count=5) then
            count <= 0;
            state <= 2;
        else
            count <= count + 1;
            Red <= '0';
            Green <= '1';
            Yellow <= '0';
        end if;
       
        when 2 =>  --Yellow Light
        if(count=2) then
            count <= 0;
            state <= 0;
        else
            count <= count + 1;
            Red <= '0';
            Green <= '0';
            Yellow <= '1';
        end if;

        when others =>
            state <= 0;
            count <= 0;
        end case;
        end if;
    end process;
end Behavioral;

CODE : DLATCH VHDL

This code is just an example for more detailed understanding of VHDL concepts I would recommend these two books :

1) A VHDL PRIMER by J. Bhasker - A VHDL PRIMER from flipkart.com
A VHDL PRIMER from amazon.com
A VHDL PRIMER from amazon.in

2)VHDL:PROGRAMMING BY EXAMPLES by PERRY - VHDL:PROGRAMMING BY EXAMPLES by PERRY from flipkart.com
VHDL:PROGRAMMING BY EXAMPLES by PERRY from amazon.com
VHDL:PROGRAMMING BY EXAMPLES by PERRY from amazon.in

CODE  : DLATCH

----------------------------------------------------------------------------------

-- Company:

-- Engineer:

-- Create Date:    20:43:29 10/31/2006

-- Design Name:

-- Module Name:    dlatch_code - Behavioral

-- Project Name:

-- Target Devices:

-- Tool versions:

-- Description:

--

-- Dependencies:

--

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

--

----------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity dlatch_code is

            Port(din,clk:in std_logic;

                          En,rst: in std_logic;

                        Q: out std_logic);      

end dlatch_code;

architecture Behavioral of dlatch_code is

begin

process(En,Din,rst,clk)

begin

if(rst='1')then

            Q<='0';

elsif(clk='1' and En='1') then

            Q<=Din;

end if;

end process;

end Behavioral;

CODE : REGISTER VHDL

CODE : REGISTER


This code is just an example for more detailed understanding of VHDL concepts I would recommend these two books :

1) A VHDL PRIMER by J. Bhasker - A VHDL PRIMER from flipkart.com
A VHDL PRIMER from amazon.com
A VHDL PRIMER from amazon.in

2)VHDL:PROGRAMMING BY EXAMPLES by PERRY - VHDL:PROGRAMMING BY EXAMPLES by PERRY from flipkart.com
VHDL:PROGRAMMING BY EXAMPLES by PERRY from amazon.com
VHDL:PROGRAMMING BY EXAMPLES by PERRY from amazon.in

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    23:57:49 11/01/2006
-- Design Name:
-- Module Name:    register_code - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity register_code is
    Port ( Din : in  STD_LOGIC_VECTOR (3 downto 0);
           clk : in  STD_LOGIC;
           rst : in  STD_LOGIC;
           Q : inout  STD_LOGIC_VECTOR (3 downto 0));
end register_code;

architecture Behavioral of register_code is

begin
    process(clk)
    begin
        if rst = '1' then
            Q <= "0000";
        elsif clk'event and clk='1' then
            Q <= Din;
        end if;
    end process;

end Behavioral;

CODE : Binary to Gray Code Converter VHDL

CODE : Binary to Gray Code Converter

This code is just an example for more detailed understanding of VHDL concepts I would recommend these two books :

1) A VHDL PRIMER by J. Bhasker - A VHDL PRIMER from flipkart.com
A VHDL PRIMER from amazon.com
A VHDL PRIMER from amazon.in

2)VHDL:PROGRAMMING BY EXAMPLES by PERRY - VHDL:PROGRAMMING BY EXAMPLES by PERRY from flipkart.com
VHDL:PROGRAMMING BY EXAMPLES by PERRY from amazon.com
VHDL:PROGRAMMING BY EXAMPLES by PERRY from amazon.in

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    10:08:01 11/06/2006
-- Design Name:
-- Module Name:    bintogray_code - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity bintogray_code is
    port(i:in std_logic_vector(3 downto 0);
         o:out std_logic_vector(3 downto 0);
           e:in std_logic);
end bintogray_code;

architecture Behavioral of bintogray_code is
begin
    process(i,e)
    begin
        if e='1' then
        o(0)<= i(0) xor i(1);
        o(1)<= i(1) xor i(2);
        o(2)<= i(2) xor i(3);
        o(3)<= i(3);
    else
        o <= "ZZZZ";
    end if;
end process;
end Behavioral;

CODE : 4X2 ENCODER VHDL

CODE : 4X2 ENCODER


This code is just an example for more detailed understanding of VHDL concepts I would recommend these two books :

1) A VHDL PRIMER by J. Bhasker - A VHDL PRIMER from flipkart.com
A VHDL PRIMER from amazon.com
A VHDL PRIMER from amazon.in

2)VHDL:PROGRAMMING BY EXAMPLES by PERRY - VHDL:PROGRAMMING BY EXAMPLES by PERRY from flipkart.com
VHDL:PROGRAMMING BY EXAMPLES by PERRY from amazon.com
VHDL:PROGRAMMING BY EXAMPLES by PERRY from amazon.in

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    21:39:58 10/31/2006
-- Design Name:
-- Module Name:    enc4X2_code - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity enc4X2_code is
    Port ( i : in  STD_LOGIC_VECTOR (3 downto 0);
           o : out  STD_LOGIC_VECTOR (1 downto 0);
           e : in  STD_LOGIC);
end enc4X2_code;

architecture Behavioral of enc4X2_code is
--signal temp : std_logic_vector(1 downto 0);
begin
process(i,e)
begin
--temp<="ZZ";
if(e='1') then
    case i is
        when "0001"=>o<="00";
        when "0010"=>o<="01";
        when "0100"=>o<="10";
        when "1000"=>o<="11";
        when others=>o<="ZZ";
    end case;
end if;


end process;


end Behavioral;