CODE : DLATCH VHDL

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CODE  : DLATCH

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-- Company:

-- Engineer:

-- Create Date:    20:43:29 10/31/2006

-- Design Name:

-- Module Name:    dlatch_code - Behavioral

-- Project Name:

-- Target Devices:

-- Tool versions:

-- Description:

--

-- Dependencies:

--

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

--

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity dlatch_code is

            Port(din,clk:in std_logic;

                          En,rst: in std_logic;

                        Q: out std_logic);      

end dlatch_code;

architecture Behavioral of dlatch_code is

begin

process(En,Din,rst,clk)

begin

if(rst='1')then

            Q<='0';

elsif(clk='1' and En='1') then

            Q<=Din;

end if;

end process;

end Behavioral;