CODE : REGISTER VHDL

CODE : REGISTER


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-- Company:
-- Engineer:
--
-- Create Date:    23:57:49 11/01/2006
-- Design Name:
-- Module Name:    register_code - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity register_code is
    Port ( Din : in  STD_LOGIC_VECTOR (3 downto 0);
           clk : in  STD_LOGIC;
           rst : in  STD_LOGIC;
           Q : inout  STD_LOGIC_VECTOR (3 downto 0));
end register_code;

architecture Behavioral of register_code is

begin
    process(clk)
    begin
        if rst = '1' then
            Q <= "0000";
        elsif clk'event and clk='1' then
            Q <= Din;
        end if;
    end process;

end Behavioral;