CODE : BCD COUNTER VHDL

CODE : BCD COUNTER

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-- Company:
-- Engineer:
--
-- Create Date:    23:45:17 11/01/2006
-- Design Name:
-- Module Name:    BCDcounter_code - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity BCDcounter_code is
    Port ( count:inout std_logic_vector(3 downto 0);
            clk  :in std_logic;
              rst  :in std_logic);
end BCDcounter_code;

architecture Behavioral of BCDcounter_code is
begin
process(clk,rst)
begin
    if rst='1' then
        count <= "0000";
    elsif clk'event and clk='1' then
        if count = "1001" then
            count <= "0000";
        else
            count <= (count+1);
        end if;
    end if;
end process;

end architecture;