Thursday, April 18, 2013

C/C++ interview question --- question 3

Why we define pointer with a type in C?

A pointer only contains an address then why do we need different data types for it ? why not a single data type for all pointers?

ANS:

Pointer data type is used in pointer arithmetic.

e.g. :

int * p1;
char * p2;

p1 = p1 + 1;
p2 = p2 +1;

value of p1 increases by sizeof(int) which is 2 bytes and p2 increases by sizeof(char) which is 1 bytes.

Saturday, April 13, 2013

C/C++ interview question --- question 2

What are the disadvantages of inlining all functions in C?

few reasons why it would be a bad idea:

Code size increases greatly especially when inlining large functions

Instruction caches become much less effective because you are always fetching new instructions from higher up in the memory hierarchy and never re-using instructions.

Register spilling would increase the stack usage but then, if you just had normal functions, you would have to pop/push activation records onto the stack instead of spilling. So, this last tradeoff is highly dependent on the code and the compiler.

HOW TO START PREPARATION FOR IAS

HOW TO START PREPARATION

As per your sugestions.......m discussing this query again.....

I WILL DISCUSS IT SECTION WISE........lets start wid INDIAN POLITY

Start with DD Basu nd then Subhash Kashyap by NBT.

Then “Perspectives On Indian Constitution” edited by Subhash Kashyap.

Indian Constitution At Work (NCERT Class XI textbook in political science, newer syllabus)

Politics in India since Independence( NCERT Class XII textbook in political science, newer syllabus)

Democracy in India: Issues and Challenges (NCERT Class XIIth textbook in Political science, older syllabus)

Democratic politics (NCERT Class Xth, newer syllabus)

**Modern History-

Began with ‘Modern India’ by Bipin Chandra, supplemented by ‘India’s struggle for Independence’ by Bipin Chandra, Mukherjee, Panikkar. Spectrum’s book on Modern India

For Ancient India, :::-- ‘Ancient India’ by R.S. Sharma (a wonderfully concise book where every single word is important) and supplemented sparsely by
‘TheWonder that was India’ by A.L. Basham.
For Medieval India, Satish Chandra’s two volumes on Medieval India quite sufficient.

Apart from this, another famous standard text is ‘An Advanced History of India’ by Majumdar, Raychaudhuri and Dutta.

--Geography

Mapping has come out to be a real challenge in recent years. The strategy to handle India map question is again practice. What one should do is to practice map everyday for one hour. Start from mountains first day, then rivers, then waterfalls and then important cities and so on. Also mark important places which are in news from news paper. Regular practice of mapping will make you more confidant. Go through atlas also

Magzine 'Geography and you' is must read, ‘Geography And You’ is available in printed as well as PDF format.

For general geography and world geography the same wizard book on geography will be more than sufficient. Special editions on these topics are published in Competition Wizard magazine which can be helpful for quick revision (only for prelims)

Indian Economy Special Issue by Pratiyogita Darpan especially for prelims.

For reference- Indian Economy by Mishra and Puri.

International affairs/ Bilateral Issues-

Contemporary World Politics( Class XIIth NCERT)

International relations chapters in the book

Democracy in India: Issues and Challenges (NCERT Class XIIth textbook in Political Science, older syllabus)

Science and technology

Science and technology section is very vast and unpredictable. . Whatever can be covered from newspapers should be done. Defence, environment, nuclear and space science are some important sections which need special emphasis.

Monthly Magzines
Pritiyogita Darpan (PD), Competition wizard and Civil services times

As far as newspaper is concerned, HINDU is ultimate

Best way to do calculations on linux console

I always used shell to do all calculation stuff but using it can be sometimes can be a little tricky.

Then I came across python doing calculations on python is very very simple.

Example :

console[1] python
Python 2.4.3 (#1, Dec 22 2011, 12:12:01)
[GCC 4.1.2 20080704 (Red Hat 4.1.2-50)] on linux2
Type "help", "copyright", "credits" or "license" for more information.
>>> t1 = 32*60 +8.1
>>> t2 = 33 *60 +35.1
>>> (t2-t1)/t2
0.043174036027988687
>>>

So you just have to type python and start doing calculations.

Friday, April 12, 2013

command to view memory and processor details in linux

To view cpu info and memory info in linux you can simply cat the related proc files.

cat /proc/cpuinfo -- for cpuinfo

cat /proc/meminfo -- for memory info
For example :

the command :
cat /proc/cpuinfo

will give output :

cat /proc/cpuinfo

processor       : 0
vendor_id       : GenuineIntel
cpu family      : 6
model           : 7
model name      : Intel(R) Xeon(R) CPU           E5450 @ 3.00GHz
stepping        : 10
cpu MHz         : 3000.114
cache size      : 6144 KB
physical id     : 0
siblings        : 4
core id         : 0
cpu cores       : 4
fpu             : yes
fpu_exception   : yes
cpuid level     : 13
wp              : yes
flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall lm pni monitor ds_cpl est tm2 cx16 xtpr lahf_lm
bogomips        : 6004.26
clflush size    : 64
cache_alignment : 64
address sizes   : 38 bits physical, 48 bits virtual
power management:
processor       : 1
vendor_id       : GenuineIntel
cpu family      : 6
model           : 7
model name      : Intel(R) Xeon(R) CPU           E5450 @ 3.00GHz
stepping        : 10
cpu MHz         : 3000.114
cache size      : 6144 KB
physical id     : 1
siblings        : 4
core id         : 4
cpu cores       : 4
fpu             : yes
fpu_exception   : yes
cpuid level     : 13
wp              : yes
flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall lm pni monitor ds_cpl est tm2 cx16 xtpr lahf_lm
bogomips        : 6000.25
clflush size    : 64
cache_alignment : 64
address sizes   : 38 bits physical, 48 bits virtual
power management:
processor       : 2
vendor_id       : GenuineIntel
cpu family      : 6
model           : 7
model name      : Intel(R) Xeon(R) CPU           E5450 @ 3.00GHz
stepping        : 10
cpu MHz         : 3000.114
cache size      : 6144 KB
physical id     : 0
siblings        : 4
core id         : 2
cpu cores       : 4
fpu             : yes
fpu_exception   : yes
cpuid level     : 13
wp              : yes
flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall lm pni monitor ds_cpl est tm2 cx16 xtpr lahf_lm
bogomips        : 6043.37
clflush size    : 64
cache_alignment : 64
address sizes   : 38 bits physical, 48 bits virtual
power management:
processor       : 3
vendor_id       : GenuineIntel
cpu family      : 6
model           : 7
model name      : Intel(R) Xeon(R) CPU           E5450 @ 3.00GHz
stepping        : 10
cpu MHz         : 3000.114
cache size      : 6144 KB
physical id     : 1
siblings        : 4
core id         : 6
cpu cores       : 4
fpu             : yes
fpu_exception   : yes
cpuid level     : 13
wp              : yes
flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall lm pni monitor ds_cpl est tm2 cx16 xtpr lahf_lm
bogomips        : 6000.28
clflush size    : 64
cache_alignment : 64
address sizes   : 38 bits physical, 48 bits virtual
power management:
processor       : 4
vendor_id       : GenuineIntel
cpu family      : 6
model           : 7
model name      : Intel(R) Xeon(R) CPU           E5450 @ 3.00GHz
stepping        : 10
cpu MHz         : 3000.114
cache size      : 6144 KB
physical id     : 0
siblings        : 4
core id         : 1
cpu cores       : 4
fpu             : yes
fpu_exception   : yes
cpuid level     : 13
wp              : yes
flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall lm pni monitor ds_cpl est tm2 cx16 xtpr lahf_lm
bogomips        : 6000.17
clflush size    : 64
cache_alignment : 64
address sizes   : 38 bits physical, 48 bits virtual
power management:
processor       : 5
vendor_id       : GenuineIntel
cpu family      : 6
model           : 7
model name      : Intel(R) Xeon(R) CPU           E5450 @ 3.00GHz
stepping        : 10
cpu MHz         : 3000.114
cache size      : 6144 KB
physical id     : 1
siblings        : 4
core id         : 5
cpu cores       : 4
fpu             : yes
fpu_exception   : yes
cpuid level     : 13
wp              : yes
flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall lm pni monitor ds_cpl est tm2 cx16 xtpr lahf_lm
bogomips        : 6000.25
clflush size    : 64
cache_alignment : 64
address sizes   : 38 bits physical, 48 bits virtual
power management:
processor       : 6
vendor_id       : GenuineIntel
cpu family      : 6
model           : 7
model name      : Intel(R) Xeon(R) CPU           E5450 @ 3.00GHz
stepping        : 10
cpu MHz         : 3000.114
cache size      : 6144 KB
physical id     : 0
siblings        : 4
core id         : 3
cpu cores       : 4
fpu             : yes
fpu_exception   : yes
cpuid level     : 13
wp              : yes
flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall lm pni monitor ds_cpl est tm2 cx16 xtpr lahf_lm
bogomips        : 6000.20
clflush size    : 64
cache_alignment : 64
address sizes   : 38 bits physical, 48 bits virtual
power management:
processor       : 7
vendor_id       : GenuineIntel
cpu family      : 6
model           : 7
model name      : Intel(R) Xeon(R) CPU           E5450 @ 3.00GHz
stepping        : 10
cpu MHz         : 3000.114
cache size      : 6144 KB
physical id     : 1
siblings        : 4
core id         : 7
cpu cores       : 4
fpu             : yes
fpu_exception   : yes
cpuid level     : 13
wp              : yes
flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall lm pni monitor ds_cpl est tm2 cx16 xtpr lahf_lm
bogomips        : 6000.24
clflush size    : 64
cache_alignment : 64
address sizes   : 38 bits physical, 48 bits virtual
power management:

Hard Disk Drive (HDD) not working on windows 7 after formatting it on Ubuntu ?

I formatted my Western Digital 500 Gb hard disk on Ubuntu 10.4 and now I want to use it on Windows 7 but it cannot detect it.
I formatted it with FAT(applicable to all) option.
I tried to Google this problem a bit and as suggested by one of the site i tried to format this drive with NTFS. Still windows cannot detect it.
Drives in windows 7 is not a problem because I tried a different usb drive on it and it works.
I can see the led of the drive glow when I connect it and I can also see remove drive safely option in lower right corner, but i cannot see any option in "my computer" to access the hard disk.

Solution:

I tried to format my HDD using "diskpart" utility available on widows7. It is working now.
Just run "diskpart" on command-promt on diskpart select your HDD and run following commands:

CLEAN
CREATE PARTITION PRIMARY 
SELECT PARTITION 1
ACTIVE
FORMAT FS=FAT32 QUICK
ASSIGN
EXIT

Sunday, April 7, 2013

CODE : ALU Arithmatic Logic Unit VHDL

This code is just an example for more detailed understanding of VHDL concepts I would recommend these two books :

1) A VHDL PRIMER by J. Bhasker - A VHDL PRIMER from flipkart.com
A VHDL PRIMER from amazon.com
A VHDL PRIMER from amazon.in

2)VHDL:PROGRAMMING BY EXAMPLES by PERRY - VHDL:PROGRAMMING BY EXAMPLES by PERRY from flipkart.com
VHDL:PROGRAMMING BY EXAMPLES by PERRY from amazon.com
VHDL:PROGRAMMING BY EXAMPLES by PERRY from amazon.in

CODE : ALU

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    23:35:34 11/01/2006
-- Design Name:
-- Module Name:    alu_code - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity alu_code is
    Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
           B : in STD_LOGIC_VECTOR (3 downto 0);
           rst : in STD_LOGIC;
            sel : in STD_LOGIC_VECTOR (2 downto 0);
           carry : out STD_LOGIC;
           o : out STD_LOGIC_VECTOR (3 downto 0);
           en : in STD_LOGIC);
end alu_code;

architecture Behavioral of alu_code is

begin
    process(sel)
    begin
        if rst='1' then
            o<="0000";
        elsif (en='1') then
            case sel is
                when "000"=> o<=(A or B);
                when "001"=> o<=(A and B);
                when "010"=> o<=(not A);
                when "011"=> o<=(A xor B);
                when "100"=> o<=(A+B);
                                if (A+B = "1111") then
                                    carry<='1';
                                else
                                    carry<='0';
                                end if;
                when "101"=> o<=(A-B);
                                if (A<B) then
                                    carry<='1';
                                else
                                    carry<='0';
                                end if;
                when "110"=> o<=(A+1);
                                if(A="1111") then
                                    carry<='1';
                                else
                                    carry<='0';
                                end if;
                when "111"=> o<=A;
                when others => o<=A;
                                    carry<='0';
           end case;
        end if;
end process;

end Behavioral;

CODE : SIPO Serial In Parallel out register VHDL

CODE : SIPO

This code is just an example for more detailed understanding of VHDL concepts I would recommend these two books :

1) A VHDL PRIMER by J. Bhasker - A VHDL PRIMER from flipkart.com
A VHDL PRIMER from amazon.com
A VHDL PRIMER from amazon.in

2)VHDL:PROGRAMMING BY EXAMPLES by PERRY - VHDL:PROGRAMMING BY EXAMPLES by PERRY from flipkart.com
VHDL:PROGRAMMING BY EXAMPLES by PERRY from amazon.com
VHDL:PROGRAMMING BY EXAMPLES by PERRY from amazon.in

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    00:06:03 11/02/2006
-- Design Name:
-- Module Name:    SIPO_code - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity SIPO_code is
    Port ( Din : in STD_LOGIC;
           o : out STD_LOGIC_VECTOR (3 downto 0);
           clk : in STD_LOGIC);
end SIPO_code;

architecture Behavioral of SIPO_code is

begin
process(clk)
variable temp: std_logic_vector(3 downto 0):="0000";
begin
    if(clk'event and clk='1') then
        temp(3):= temp(2);
        temp(2):= temp(1);
        temp(1):= temp(0);
        temp(0):=Din;
        o<=temp;
    end if;
end process;

end Behavioral;

CODE : 4 Bit Data Demultiplexer VHDL

CODE : 4 Bit Data Demultiplexer

This code is just an example for more detailed understanding of VHDL concepts I would recommend these two books :

1) A VHDL PRIMER by J. Bhasker - A VHDL PRIMER from flipkart.com
A VHDL PRIMER from amazon.com
A VHDL PRIMER from amazon.in

2)VHDL:PROGRAMMING BY EXAMPLES by PERRY - VHDL:PROGRAMMING BY EXAMPLES by PERRY from flipkart.com
VHDL:PROGRAMMING BY EXAMPLES by PERRY from amazon.com
VHDL:PROGRAMMING BY EXAMPLES by PERRY from amazon.in

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    10:47:38 11/06/2006
-- Design Name:
-- Module Name:    Demux_code - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Demux_code is
port( din   :in std_logic_vector(3 downto 0);
         sel   :in std_logic_vector(1 downto 0);
            dout1, dout2,dout3 :out std_logic_vector(3 downto 0));
end Demux_code;

architecture Behavioral of Demux_code is
begin
process(din,sel)
begin
    case sel is
        when "00"=> dout1<=din;
                    dout2<="ZZZZ";
                    dout3<="ZZZZ";
        when "01"=> dout1<="ZZZZ";
                    dout2<=din;
                    dout3<="ZZZZ";
        when others=>dout1<="ZZZZ";
                     dout2<="ZZZZ";
                     dout3<=din;
    end case;
end process;
end Behavioral;

CODE : BCD COUNTER VHDL

CODE : BCD COUNTER

This code is just an example for more detailed understanding of VHDL concepts I would recommend these two books :

1) A VHDL PRIMER by J. Bhasker - A VHDL PRIMER from flipkart.com
A VHDL PRIMER from amazon.com
A VHDL PRIMER from amazon.in

2)VHDL:PROGRAMMING BY EXAMPLES by PERRY - VHDL:PROGRAMMING BY EXAMPLES by PERRY from flipkart.com
VHDL:PROGRAMMING BY EXAMPLES by PERRY from amazon.com
VHDL:PROGRAMMING BY EXAMPLES by PERRY from amazon.in

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    23:45:17 11/01/2006
-- Design Name:
-- Module Name:    BCDcounter_code - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity BCDcounter_code is
    Port ( count:inout std_logic_vector(3 downto 0);
            clk :in std_logic;
            rst :in std_logic);
end BCDcounter_code;

architecture Behavioral of BCDcounter_code is
begin
process(clk,rst)
begin
    if rst='1' then
        count <= "0000";
    elsif clk'event and clk='1' then
        if count = "1001" then
            count <= "0000";
        else
            count <= (count+1);
        end if;
    end if;
end process;

end architecture;

CODE : TRAFFIC LIGHT CONTROLLER VHDL

CODE : TRAFFIC LIGHT CONTROLLER

This code is just an example for more detailed understanding of VHDL concepts I would recommend these two books :

1) A VHDL PRIMER by J. Bhasker - A VHDL PRIMER from flipkart.com
A VHDL PRIMER from amazon.com
A VHDL PRIMER from amazon.in

2)VHDL:PROGRAMMING BY EXAMPLES by PERRY - VHDL:PROGRAMMING BY EXAMPLES by PERRY from flipkart.com
VHDL:PROGRAMMING BY EXAMPLES by PERRY from amazon.com
VHDL:PROGRAMMING BY EXAMPLES by PERRY from amazon.in

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    00:24:35 11/02/2006
-- Design Name:
-- Module Name:    tfcontroller_code - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity tfcontroller_code is
    Port ( clk : in STD_LOGIC;
           rst : in STD_LOGIC;
           Green : out STD_LOGIC;
           Red : out STD_LOGIC;
           Yellow : out STD_LOGIC);
end tfcontroller_code;

architecture Behavioral of tfcontroller_code is

signal count:integer range 0 to 10 := 0;
signal state:integer range 0 to 2 := 0;
begin
    process(clk, rst)
    begin
        if(rst = '1') then
            state <= 0;
            Red <= '1';
            Green <= '0';
            Yellow <= '0';
            count <= 0;
        elsif clk'event and clk='1' then
        case state is
        when 0 => --Red Light
        if(count=5) then
            count <= 0;
            state <= 1;
        else
            count <= (count + 1);
            Red <= '1';
            Green <= '0';
            Yellow <= '0';
        end if;

        when 1 => --Green Light
        if(count=5) then
            count <= 0;
            state <= 2;
        else
            count <= count + 1;
            Red <= '0';
            Green <= '1';
            Yellow <= '0';
        end if;

        when 2 => --Yellow Light
        if(count=2) then
            count <= 0;
            state <= 0;
        else
            count <= count + 1;
            Red <= '0';
            Green <= '0';
            Yellow <= '1';
        end if;

        when others =>
            state <= 0;
            count <= 0;
        end case;
        end if;
    end process;
end Behavioral;

CODE : DLATCH VHDL

CODE : DLATCH

----------------------------------------------------------------------------------

-- Company:

-- Engineer:

-- Create Date: 20:43:29 10/31/2006

-- Design Name:

-- Module Name: dlatch_code - Behavioral

-- Project Name:

-- Target Devices:

-- Tool versions:

-- Description:

-- Dependencies:

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

----------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity dlatch_code is

Port(din,clk:in std_logic;

En,rst: in std_logic;

Q: out std_logic);

end dlatch_code;

architecture Behavioral of dlatch_code is

begin

process(En,Din,rst,clk)

begin

if(rst='1')then

Q<='0';

elsif(clk='1' and En='1') then

Q<=Din;

end if;

end process;

end Behavioral;

CODE : REGISTER VHDL

CODE : REGISTER

This code is just an example for more detailed understanding of VHDL concepts I would recommend these two books :

1) A VHDL PRIMER by J. Bhasker - A VHDL PRIMER from flipkart.com
A VHDL PRIMER from amazon.com
A VHDL PRIMER from amazon.in

2)VHDL:PROGRAMMING BY EXAMPLES by PERRY - VHDL:PROGRAMMING BY EXAMPLES by PERRY from flipkart.com
VHDL:PROGRAMMING BY EXAMPLES by PERRY from amazon.com
VHDL:PROGRAMMING BY EXAMPLES by PERRY from amazon.in

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    23:57:49 11/01/2006
-- Design Name:
-- Module Name:    register_code - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity register_code is
    Port ( Din : in STD_LOGIC_VECTOR (3 downto 0);
           clk : in STD_LOGIC;
           rst : in STD_LOGIC;
           Q : inout STD_LOGIC_VECTOR (3 downto 0));
end register_code;

architecture Behavioral of register_code is

begin
    process(clk)
    begin
        if rst = '1' then
            Q <= "0000";
        elsif clk'event and clk='1' then
            Q <= Din;
        end if;
    end process;

end Behavioral;

CODE : Binary to Gray Code Converter VHDL

CODE : Binary to Gray Code Converter

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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    10:08:01 11/06/2006
-- Design Name:
-- Module Name:    bintogray_code - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity bintogray_code is
    port(i:in std_logic_vector(3 downto 0);
         o:out std_logic_vector(3 downto 0);
           e:in std_logic);
end bintogray_code;

architecture Behavioral of bintogray_code is
begin
    process(i,e)
    begin
        if e='1' then
        o(0)<= i(0) xor i(1);
        o(1)<= i(1) xor i(2);
        o(2)<= i(2) xor i(3);
        o(3)<= i(3);
    else
        o <= "ZZZZ";
    end if;
end process;
end Behavioral;