1) A VHDL PRIMER by J. Bhasker - A VHDL PRIMER from flipkart.com
A VHDL PRIMER from amazon.com
A VHDL PRIMER from amazon.in
2)VHDL:PROGRAMMING BY EXAMPLES by PERRY - VHDL:PROGRAMMING BY EXAMPLES by PERRY from flipkart.com
VHDL:PROGRAMMING BY EXAMPLES by PERRY from amazon.com
VHDL:PROGRAMMING BY EXAMPLES by PERRY from amazon.in
CODE : ALU
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:35:34 11/01/2006
-- Design Name:
-- Module Name: alu_code - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity alu_code is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
rst : in STD_LOGIC;
sel : in STD_LOGIC_VECTOR (2 downto 0);
carry : out STD_LOGIC;
o : out STD_LOGIC_VECTOR (3 downto 0);
en : in STD_LOGIC);
end alu_code;
architecture Behavioral of alu_code is
begin
process(sel)
begin
if rst='1' then
o<="0000";
elsif (en='1') then
case sel is
when "000"=> o<=(A or B);
when "001"=> o<=(A and B);
when "010"=> o<=(not A);
when "011"=> o<=(A xor B);
when "100"=> o<=(A+B);
if (A+B = "1111") then
carry<='1';
else
carry<='0';
end if;
when "101"=> o<=(A-B);
if (A<B) then
carry<='1';
else
carry<='0';
end if;
when "110"=> o<=(A+1);
if(A="1111") then
carry<='1';
else
carry<='0';
end if;
when "111"=> o<=A;
when others => o<=A;
carry<='0';
end case;
end if;
end process;
end Behavioral;
No comments:
Post a Comment