2X4 DECODER VHDL

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CODE : 2X4 DECODER

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-- Company:

-- Engineer:

--

-- Create Date:    21:18:08 10/31/2006

-- Design Name:

-- Module Name:    2X4dec_code - Behavioral

-- Project Name:

-- Target Devices:

-- Tool versions:

-- Description:

--

-- Dependencies:

--

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

--

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity dec2X4_code is

    Port ( i : in  STD_LOGIC_VECTOR (1 downto 0);

           e : in  STD_LOGIC;

           o : out  STD_LOGIC_VECTOR (3 downto 0));

end dec2X4_code;

architecture Behavioral of dec2X4_code is

begin

            process(i,e)

            begin

                        if(e='1') then

                                    o(0) <= not(i(0)) and not(i(1));

                                    o(1) <= (i(0)) and not(i(1));

                                    o(2) <= not(i(0)) and i(1);

                                    o(3) <= i(0) and i(1);

                        else

                                    o <= "ZZZZ";

                        end if;

            end process;

end Behavioral;