CODE : Binary to Gray Code Converter VHDL

CODE : Binary to Gray Code Converter

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-- Company:
-- Engineer:
--
-- Create Date:    10:08:01 11/06/2006
-- Design Name:
-- Module Name:    bintogray_code - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity bintogray_code is
    port(i:in std_logic_vector(3 downto 0);
         o:out std_logic_vector(3 downto 0);
           e:in std_logic);
end bintogray_code;

architecture Behavioral of bintogray_code is
begin
    process(i,e)
    begin
        if e='1' then
        o(0)<= i(0) xor i(1);
        o(1)<= i(1) xor i(2);
        o(2)<= i(2) xor i(3);
        o(3)<= i(3);
    else
        o <= "ZZZZ";
    end if;
end process;
end Behavioral;