CODE : 4X2 ENCODER VHDL

CODE : 4X2 ENCODER


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-- Company:
-- Engineer:
--
-- Create Date:    21:39:58 10/31/2006
-- Design Name:
-- Module Name:    enc4X2_code - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity enc4X2_code is
    Port ( i : in  STD_LOGIC_VECTOR (3 downto 0);
           o : out  STD_LOGIC_VECTOR (1 downto 0);
           e : in  STD_LOGIC);
end enc4X2_code;

architecture Behavioral of enc4X2_code is
--signal temp : std_logic_vector(1 downto 0);
begin
process(i,e)
begin
--temp<="ZZ";
if(e='1') then
    case i is
        when "0001"=>o<="00";
        when "0010"=>o<="01";
        when "0100"=>o<="10";
        when "1000"=>o<="11";
        when others=>o<="ZZ";
    end case;
end if;


end process;


end Behavioral;