CODE : 4 Bit Data Demultiplexer VHDL

CODE : 4 Bit Data Demultiplexer

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-- Company:
-- Engineer:
--
-- Create Date:    10:47:38 11/06/2006
-- Design Name:
-- Module Name:    Demux_code - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Demux_code is
  port(  din   :in std_logic_vector(3 downto 0);
         sel   :in std_logic_vector(1 downto 0);
            dout1, dout2,dout3  :out std_logic_vector(3 downto 0));
end Demux_code;

architecture Behavioral of Demux_code is
begin
process(din,sel)
begin
    case sel is
        when "00"=> dout1<=din;
                    dout2<="ZZZZ";
                    dout3<="ZZZZ";
        when "01"=> dout1<="ZZZZ";
                    dout2<=din;
                    dout3<="ZZZZ";
        when others=>dout1<="ZZZZ";
                     dout2<="ZZZZ";
                     dout3<=din;
    end case;
end process;
end Behavioral;